1. Field of the Invention
The present invention relates to a method of making a semiconductor device and more particularly to a method capable of carrying out an effective interconnection between wires.
2. Description of the prior art
FIG. 1 is a sectional view showing the structure of a conventional semiconductor device.
According to FIG. 1, a first insulator(2) is formed over the entire surface of a single crystalline substrate(1) by chemical vapour deposition(CVD) method so as to isolate the device regions from wires electrically. A conductor such as aluminum is then formed over the first insulator(2). Conventionally, a plurality of device regions (not shown) are formed at the surface of the single crystaline silicon substrate. A plurality of first wires(3) are formed over the first insulator(2) by patterning the conductor with a photolithography process and an etching process.
Subsequently, over the entire exposed surfaces of the first wires(3) and the first insulator(2), a second insulator (4) for insulating first comes(3) from each other is formed using the CVD method. Thereafter, the second insulator (4) is subjected to the photolithography process and the anisotropic dry etching process, thereby forming a contact hole(5) in the second insulator(4). The contact hole (5), therefore, is the surface area disposed over the surface of a selected first wire (3) when the second insulator (4) is removed. Subsequently, a conductor such as aluminum is formed over the surfaces of the first wire(3) exposed through the contact hole(5) and over the second insulator(4) by a sputtering deposition method. The conductor is patterned by a photolithograply process and an anisotropic dry etching process so as to form a second wire(6) to be connected with the selected first wire(3) through the contact hole(5).
FIG. (2) shows the layout diagram of the semiconductor device corresponding to FIG. (1).
However, a semiconductor device having the above-mentioned conventional structure has the following problems.
First, due to the formation of the contact hole(5), the step coverage of the second wire(6) being formed using the sputtering deposition method becomes worse at a region(K.sub.1) than at other regions along the second wire(6) is thinner than that of the rest of the regions along the second wire(6) excluding region (K.sub.1), the current density at the region(K.sub.1) is higher than that of the rest of the second wire(6) excluding the region(K.sub.1) when a power source voltage is applied to the semiconductor device.
Therefore, one problem with a conventionally structured semiconductor is that the second wire(6) may be disconnected, thereby causing the reliability of the semiconductor device to be deteriorated.
Second, the fringe region(K.sub.2) (shown in FIG. 2) should be formed so as to securely connect the first wire(3) to the second wire(6). Accordingly, the space between the second wires(6) becomes too narrow. So as to overcome the above problems, an alternative method of making another semiconductor device has been suggested. This alternative method of making the semiconductor device will be described in detail hereinafter with reference to FIG. 3a through FIG. 3f.
As shown in FIG. 3a, a single crystalline silicon substrate(31) is first prepared and then a first insulator(32) for electrically isolating the device regions from wires is formed on the single crystalline silicon substrate(31) by the CVD method. Over the entire exposed surface of the first insulator (32), a first conductor (33) and a second conductor (34) are formed in this order by the sputtering deposition method. Thereafter, the first conductor(33) and the second conductor(34) are patterned by the photolithography process and the anisotropic dry etching method such as reactive ion etching (RIE), so as to form uniformly spaced a plurality of patterns(35). Each pattern(35) is comprised of a first conductor component(33a) and a second conductor component(34a).
Thereafter, a photo resist(36) is coated over a selected pattern(35) as shown in FIG. 3c and then the second conductor components(34a) of the non-selected patterns(35) removed by RIE method which is a kind of dry etching method, as shown in FIG. 3d. Thereafter, the photo resist(36) is removed.
At this time, the second conductor component(34a) of the selected pattern(35) serve as an interconnection wire and the first conductor components(33a) of all of the patterns(35) serve as first wires. As shown in FIG. 3e, a second insulator(37) is on the surface of the first insulator(32) to the surface of the second conductor component(34a) of the selected pattern(35) by a bias sputtering deposition method using a quartz target in the argon ambience, so as to electrically isolate the wires from each other.
In this time, because the sputtering of argon gas is generated simultaneously, a thin oxide is formed over the surface of the interconnection wire (the second conductor component 34a of the selected pattern 35). The surface of the interconnection wire is partially removed by the sputtering of argon gas. As a result, the interconnection wire has an inclined plane respectively at both edges of the surface. As shown in FIG. 3f, the oxide formed over the surface of the interconnection wire is removed and then a third conductor (for example aluminum) is formed over the entire surfaces of the second insulator(37) and the connection wire.
By carrying out the photolithograply process and the anisotropic etching process, the third conductor is patterned so as to form a second wire (38) to be connected to the selected first wire(the first conductor component 33a of the selected pattern 35) through the above interconnection wire(the second conductor component 34a of the selected pattern 35).
FIG. 4 is a perspective view showing a semiconductor device corresponding to FIG. 3d.
However, the above-mentioned alternative method of conventional art has the following problems. First, as shown in FIG. 3b, the first conductor(33) should be etched with an etching gas such as CF.sub.4 or SF.sub.6 and the second conductor(34) should be etched with an etching gas such as Cl.sub.z.
In other words, because the materials of the first conductor(33) and the second conductor(34) are different each other, there is an inconvenience that the etching gas should be changed in accordance with the kind of the material to be etched.
Furthermore, if the change time of the etching gas is not accurate, the shape of the first wires will be formed irregularly.
Second, so as to obtain the first conductor component(33a) of the selected pattern(35) shown in FIG. 4 representing a perspective view of FIG. 3d, the first conductor(33) should be subjected to the anisotropic dry etching process twice, thereby causing the surface of the first conductor component(33a) to be damaged.
Furthermore, since the second conductor should be also subject to the anisotropic etching process twice so as to obtain the second conductor component(34a) of the patterns(35), the scraps of the second conductor (34) may remain during the dry etching processes, thereby causing the reliability of produced semiconductor device to be deteriorated.